The present invention relates to a semiconductor device, and can be suitably used, for example, for a semiconductor device including an asynchronous successive approximation type A/D (Analog/Digital) converter.
The synchronous successive approximation type A/D converter can be realized with a relatively simple circuit configuration, but requires a clock signal that oscillates multiple times in the course of A/D conversion. However, in a high-speed system chip, a clock signal having a frequency of several times to several tens of times the frequency of a system clock signal is rarely obtained.
Therefore, there is proposed an asynchronous successive approximation type A/D converter that generates an internal clock signal by a self-loop using a delay circuit and operates in synchronization with the internal clock signal. For example, when the delay circuit is constituted of a plurality of stages of inverters coupled in series, the delay time of the delay circuit fluctuates under the conditions of temperature, processes, power supply voltages, and the like. When the delay time is excessively large, the cycle of the internal clock signal becomes excessively large and thus a desired number of times of comparison operations cannot be performed. Moreover, when the delay time is excessively small, the operation of a peripheral circuit cannot follow the internal clock. Then, Japanese Patent Laid-Open No. 2011-61597 proposes a method for counting the number of falling edges of an internal clock signal with a counter and controlling the delay time of a delay circuit on the basis of the count value.